Embodiments of the inventive concept relate generally to electronic memory technologies. More particularly, embodiments of the inventive concept relate to a memory controller for a nonvolatile memory device, a memory system comprising the memory controller, and related methods of operation.
Certain types of nonvolatile memory devices perform program and erase operations using electrical control mechanisms. For example, some nonvolatile memory devices perform program and erase operations by moving electrons across an insulating layer to change a memory cell's threshold voltage.
When programming nonvolatile memory cells by changing their threshold voltages, it is generally difficult or impossible to change the threshold voltages with absolute precision. Accordingly, different program states are generally characterized by different ranges or distributions of threshold voltages. As the threshold voltage distributions become wider, the read margins for distinguishing between different program states tend to become smaller. These smaller read margins can lead to errors and general deterioration of device performance. Such deterioration is of particular concern in multi-level cell (MLC) memory devices where there are many possible program states and relatively small read margins.
FIG. 1 is a diagram of a cell array in a conventional nonvolatile memory device 1.
Referring to FIG. 1, a memory cell MC0 is electrically influenced by adjacent or neighboring memory cells in a program operation. Due to neighboring cells MC1 through MC8, a threshold voltage of the memory cell MC0 may shift even if it is not directly programmed. Memory cells that exert the influence (e.g., MC1 through MC8), are referred to as aggressor cells and a cell that is influenced (e.g., MC0) is referred to a victim cell.
A threshold voltage may change (e.g., decrease) due to a coupling effect, lapse of time, hot temperature stress (HTS), or degradation of an oxide layer caused by an increase in a program-erase (P-E) cycle. In other words, the threshold voltage of the memory cell, i.e., the victim cell MC0 shifts by a certain level from an original threshold voltage. In another case, the threshold voltage of the memory cell MC0 may increase due to program disturbance occurring when an adjacent cell is programmed.
The charge loss in the aggressor cells MC1 through MC8 may be considered as another physical cause of the change in the threshold voltage. In another case, the distribution may be deteriorated by lateral charge spreading in which charges move to adjacent cells because of the properties of an element such as a floating gate in a charge trap flash (CTF) memory. Furthermore, adjacent cells exerting a physical influence may change with different programming methods.
The shift of the threshold voltage of the memory cell MC0 is not restricted to a particular operation or context. For example, it is not restricted to situations where memory cell MC0 is connected to the same bit line BL1 as memory cells MC3 and MC6 or the same word line WL1 as the memory cells MC1 and MC2. Due to the shift of threshold voltage, where a read operation is performed on nonvolatile memory device 1, a read margin is reduced and two adjacent distributions of threshold voltage distributions may overlap with each other. In this case, data that has been read may have error bits, which can reduce reliability and increase a failure rate.